Clock Generator PLL IP for SMIC
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Clock Generator PLL IP
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9
Clock Generator PLL IP
for SMIC
from 4 vendors
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9)
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High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
- Fractional-N digital PLL architecture, using an LC-tank oscillator
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Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
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General Purpose Fractional-N PLLs
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution
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Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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4-GHz Jitter-optimized low-power digital PLL
- - Jitter below 10-ps
- - Super small: 90 x 90 microns!
- - Very low power: 15-mW
- - Broad frequency range: 4-GHz
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Phase-locked loop system 2.8 to 3.3 GHz
- SMIC CMOS 0.18 um
- Wide frequency range (2.8…3.3 GHz)
- Built-in switched capacitors sections for VCO frequency adjustment
- Low noise figure
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4-GHz Jitter-optimized low-power digital PLL
- Jitter below 10-ps
- Super small: 90 x 90 microns!
- Very low power: 15-mW
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SMIC 28nm High-K 1.8V/0.9V PLL
- Process:SMIC 28nm High-k 1.8V/0.9V process
- Supply voltage: 1.62V<=AVDD<=1.98V,0.81V<=DVDD(AVDD2)<=0.99
- Mos device type: nfet, pfet, egnfet, egpfet, mom_2t
- Operating current: AVDD<1.2mA(1GHz) AVDD<4.8mA(3.2GHz)