Clock Generator PLL IP for Samsung
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Clock Generator PLL IP
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10
Clock Generator PLL IP
for Samsung
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Fractional-N Frequency Synthesizer PLL
- Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
- Input & output frequency ranges greater than 1000:1
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High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
- Fractional-N digital PLL architecture, using an LC-tank oscillator
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Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
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General Purpose Fractional-N PLLs
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution
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High Performance Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP for 5G, WiFi, etc
- Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
- Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
- Small die area (< 0.05 sq mm), using a LC tank oscillator
- Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
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Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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Fractional-N PLL for Performance Computing in Samsung 14LPP
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.004 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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Fractional-N PLL for Performance Computing in Samsung 8LPP
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.003 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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High Performance Fractional-N RF Frequency Synthesizer PLL in Samsung 8LPP for 5G, WiFi, etc
- Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
- Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
- Small die area (< 0.05 sq mm), using a LC tank oscillator
- Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
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Samsung 28nm FDSOI 1.8v/1.0v APLL
- Process: Samsung 28nm FDSOI 1.0v1.8v process
- Supply voltage: 1.62V<=AVDD<=1.98V, 0.9V<=DVDD(AVDD2)<=1.1V
- Mos device: pfet, nfet, egpfet, egnfet, vncap, rpposab
- Operating current:AVDD<4mA(2.4GHz)