Processor IP

Compare 699 Processor IP from 125 vendors (1 - 10)

General Purpose Neural Processing Unit (NPU)
- Hybrid Von Neuman + 2D SIMD matrix architecture
- 64b Instruction word, single instruction issue per clock
- 7-stage, in-order pipeline
32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
NPU IP for Embedded AI
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
RISC-V-based AI IP development for enhanced training and inference
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
ComputeRAM
- Available as a 18 kB macro in GlobalFoundries 22FDX process; - Memory Compiler and FinFET variants under development
- Low power sleep mode with data retention
- Built using proven foundry SRAM bit cells, fully CMOS, strictly obeys foundry DFM/DRC rules
- Bit-accurate computation
IP cores for ultra-low power AI-enabled devices
- Ultra-fast Response Time
- Zero-latency Switching
- Low Power
64-bit RISC-V Application Processor Core
- 64-bit RISC-V core
- Linux capable
- In-order 7-stage pipeline
32 Bit - Embedded RISC-V Processor Core
- 32 bit,
- 3-stage pipeline,
- 32 registers
32 bit - Compact RISC-V Processor Core
- 32-bit RISC-V core
- RV32EMC instruction set
- 16 general purpose registers