Slaver DLL

The INNOSILICON slaver DLL PHY provides the low power and high-speed applications and small silicon area. According to the input clock signal, an accurate 0/90/180/270 phase clock with the same frequency as the input clock can be generated. The slaver DLL PHY components support differential clock steady-state output in dynamic lock state, contain DLL specialized functional and utility DLL up to 800Mbps in SMIC 28nm, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any DLL application.