MIPI BIF Master IP

Overview

MIPI BIF Master interface provides full support for the two-wire MIPI BIF synchronous serial interface, compatible with BIF specification. Through its BIF compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI BIF Master IIP is proven in FPGA environment. The host interface of the MIPI BIF can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

Key Features

Compliant with 1.0 MIPI BIF Specification.
Full MIPI BIF Master functionality.
Supports following commands
->Reset
->Power control
->Interrupt
->Burst
->Multicast
->UID search
->Device specific command
Glitch suppression (optional).
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices.

Benefits

Single Site license option is provided to companies designing in a single site.
Multi Sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

The MIPI BIF Master interface is available in Source and netlist products.
The Source product is delivered in plain text verilog or VHDL or SystemC source code
Integration testbench and tests
Scripts for simulation and synthesis with support for common EDA tools
Documentation contains User s Guide and Release notes.

Technical Specifications

Maturity

Getting used at customer site

Request Info