56G SerDes IP core supports PAM4 signaling in the range of 25.0-60.0 Gbps using full-rate and half-rate modes with scrambled data. Non-return-to-zero (NRZ) signaling is supported in the range of 5.0-30.0 Gbps using full, half, and quarter-rate modes. Either scrambled or block coded (for example, 8B/10B) data is supported for 5.0-12.5 Gbps in NRZ mode. However, scrambled data is required for data rates greater than 12.5 Gbps.
The 56G SerDes IP cores are intended for use as a chip-to-chip or a card-to-card connection mechanism.
56G SerDes Ethernet
Overview
Key Features
- Data rate support up to 56Gbps (per lane)
- Support the following protocols: 400GAUI-8, 400GAUI-16, CEI-56G-LR, CEI-56G-MR, CEI-56G-VSR, 40GBASE-CR4, 40GBASE-KR4, 100GBASE-CR10, 100GBASE-CR4, 100GBASE-KR4
- Aggressive equalization capability to enable 56Gbps operation and legacy system upgrades
- Variable AGC amplifier
- Programmable Long Tail Equalizer (LTE)
- Digitally-control-impedance termination resistors
- Configurable TX output differential voltage swing
- On-chip AC coupling for maximum interoperability
Benefits
- Support for manufacturing and system test
- Generalized scan design compliant with manufacturing functional (macro) tests
- Full-rate loopback and Built-In Self-Tests (BIST) with selectable PRBS patterns
- Compatible with IEEE 1149.6-2003 ACJTAG
- Optimized performance, power consumption and area
- Supports Flip-Chip package
Applications
- 400/800G Communication
- Hyperscale Data Center
- AI and Machine Learning
Deliverables
- GDSII&CDL Netlist
- Verilog Model
- LEF Layout Abstract(.LEF)
- Liberty Timing Models(.lib)
- Verify Results
- Specification
- Datasheet
- Integration Guideline
- Evaluation Plan
- Leading support for package design, SI&PI modeling and production test development
Technical Specifications
Availability
Available