Low Bandwidth PLL IP
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19
Low Bandwidth PLL IP
from 5 vendors
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Integer N PLL for Frequency Synthesis
- 1 GHz–2 GHz LO frequency range
- 5 MHz–20 MHz input clock frequency range
- 9-bit programmable divider (100-511)
- 7-band VCO with off-chip resonator
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40nm 1.1V 6.0GHz-9.4GHz Fractional-N RF PLL
- TSMC 40nm CMOS
- 6.0GHz-to-9.7GHz Buffered VCO PLL Output Coverage
- Scalable Power Consumption
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40nm 1.1V 2GHz-4.7GHz Fractional-N RF Quadrature PLL
- 2.0GHz-to-4.7GHz PLL Output Coverage
- Scalable Power Consumption
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40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
- Rail-to-Rail IQ ADC Input Capability
- 65dB IQ ADC SNR
- Programmable Full-Scale IQ DAC Output Current
- 65dB IQ DAC SNR
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40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
- 16MHz-to-2GHz PLL Output Coverage
- Scalable Power Consumption
- Three independent programmable PLL outputs
- Internal Calibration Engine and Convergence Algorithm
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Fractional-N PLL for Performance Computing in GlobalFoundries 12LPP/14LPP
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.004 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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Fractional-N PLL for Performance Computing in GlobalFoundries 22FDX
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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Fractional-N PLL for Performance Computing in UMC40LP
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.02 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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Fractional-N PLL for Performance Computing in TSMC N6/N7
- Frequencies up to 4GHz
- Low jitter (< 10ps RMS)
- Small size (< 0.01 sq mm)
