SATA PHY IP for UMC
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SATA PHY IP
for UMC
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15
SATA PHY IP
for UMC
from 6 vendors
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10)
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SATA 6G PHY in UMC (40nm, 28nm, 22nm)
- Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
- AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
- AMBA 4 AXI and ACE-Lite bus interfaces
- Memory data protection and memory address parity protection
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Serial ATA (SATA) I/II PHY IP CORE
- Supports 1.5 Gb/s (Gen 1) and 3.0 Gb/s (Gen 2) serial data rate
- Compatible with Serial ATA II
- Utilizes 10-bit or 20-bit parallel interface to transmit and receive Serial ATA data
- Data and clock recovery from serial stream on the SATA bus
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PCIe 3.0/3.1/USB3.0/SATA3 Combo PHY
- Standard PHY interface enables multiple IP sources for PCI Express Logical Layer and provides a target interface for PCI Express PHY vendors.
- Supports 2.5Gb/s only or 2.5Gb/s,5.0Gb/s and 8.0Gb/s serial data transmission rate
- Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive PCI Express data
- Allows integration of high speed components into a single functional block as seen by the endpoint device designer.
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SATA 3.0 PHY
- OOB Generation and Detection
- Elasticity Buffer Optional
- Alternative Host or Device Power-on Sequence State Machine
- Speed Reduction Negotiation in Device Mode
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SATA 6G PHY
- ? 6-Gbps transmission rate through standard SATA cable
- ? Spread-spectrum clock (SSC) generation and absorption
- ? Programmable down-spread (+4,980 ppm through -4,980 ppm)
- ? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY
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Serial ATA PHY
- 1.5 / 3.0 Gbps
- Complies with SATA 3.0 Specification