PCI Express Phy IP for SMIC
Welcome to the ultimate PCI Express Phy IP for SMIC hub! Explore our vast directory of PCI Express Phy IP for SMIC
All offers in
PCI Express Phy IP
for SMIC
Filter
Compare
15
PCI Express Phy IP
for SMIC
from 4 vendors
(1
-
10)
-
PCIe 2.0 PHY in SMIC (40nm, 28nm)
- Physical coding sublayer (PCS) block with PIPE interface
- Supports PCIe power management features, including L1 substate
- Power gating for lowest standby power
- Low active power using voltage mode TX with under drive supply options
-
PCIe4/3/2/1 PHY & Controller
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
-
SGMII PHY
- General:
- Interface:
- PMA-TX:
- PMA-RX:
-
PCIe5.0 PHY & Controller
- Fully compliant with PCI Express Base Specification Revision 5.0
- Fully compliant with PIPE Specifications Revision 4.4.1
- Support Root Complex and Endpoint Mode
- Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps), Gen4 (16Gbps), Gen5 (32Gbps)
-
PCIe4.0 PHY
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
-
PCIe4.0 Controller
- Fully compliant with PCI Express Base Specification Revision 4.0.
- Fully compliant with PIPE Specifications Revision 4.4.1.
- Support Root Complex and Endpoint Mode.
- Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps), Gen4 (16Gbps)
-
PCIe3.0 PHY
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
-
PCIe3.0 Controller
- Fully compliant with PCI Express Base Specification Revision 3.0.
- Fully compliant with PIPE Specifications Revision 4.4.1
- Support Root Complex and Endpoint Mode.
- Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps)
-
PCIe2.0 PHY & Controller
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
-
JESD204B PHY & Controller
- Support for serial data rates up to 12.5Gbps
- Supports Subclass 0, 1 and 2.
- Supports 4 lanes.
- Supports 1-32 converters.