PCI IP for SMIC

Compare 23 PCI IP for SMIC from 7 vendors (1 - 10)

PCIe 3.1 Controller with AXI
- Compliant with the PCI Express 3.1/3.0, and PIPE (16- and 32-bit) specifications
- Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
- Supports Endpoint, Root-Port, Dual-mode configurations
- Supports x16, x8, x4, x2, x1 at 8 GT/s, 5 GT/s, 2.5 GT/s speeds
- Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
- Supports many ECNs including LTR, L1 PM substates, etc.
PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 14SF+
- Support for SATA3(6.0Gbps) ,USB3.0(5Gbps) and PCIe3(8.0Gbps),
- Backward compatible with 1.5Gbps, 3.0bps for SATA
- Backward compatible with 2.5Gbps and 5Gbps for PCIe
- Full compatible with PIPE4 interface specification
PCIe 3.0/3.1/USB3.0/SATA3 Combo PHY
- Standard PHY interface enables multiple IP sources for PCI Express Logical Layer and provides a target interface for PCI Express PHY vendors.
- Supports 2.5Gb/s only or 2.5Gb/s,5.0Gb/s and 8.0Gb/s serial data transmission rate
- Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive PCI Express data
- Allows integration of high speed components into a single functional block as seen by the endpoint device designer.
PCIe 2.0 PHY in SMIC (40nm, 28nm)
- Physical coding sublayer (PCS) block with PIPE interface
- Supports PCIe power management features, including L1 substate
- Power gating for lowest standby power
- Low active power using voltage mode TX with under drive supply options
PCIe4/3/2/1 PHY & Controller
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
SGMII PHY
- General:
- Interface:
- PMA-TX:
- PMA-RX:
PCIe4.0 PHY
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
PCIe3.0 PHY
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
PCIe2.0 PHY & Controller
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive: