PCI IP for SMIC

Compare 23 PCI IP for SMIC from 7 vendors (1 - 10)

PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- Complies with the PCI Express® Base 3.0 Specification, rev.3.1
- Supports Endpoint, Root-Port, Dual-Role, Switch configurations
- Supports x16, x8, x4, x2, x1 at Gen3, Gen2, Gen1 speeds
- Implements one Virtual Channel
PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
- PCIe Interface
PCIe 2.0 PHY in SMIC (40nm, 28nm)
- Physical coding sublayer (PCS) block with PIPE interface
- Supports PCIe power management features, including L1 substate
- Power gating for lowest standby power
- Low active power using voltage mode TX with under drive supply options
PCIe4/3/2/1 PHY & Controller
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
SGMII PHY
- General:
- Interface:
- PMA-TX:
- PMA-RX:
PCIe5.0 PHY & Controller
- Fully compliant with PCI Express Base Specification Revision 5.0
- Fully compliant with PIPE Specifications Revision 4.4.1
- Support Root Complex and Endpoint Mode
- Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps), Gen4 (16Gbps), Gen5 (32Gbps)
PCIe4.0 PHY
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
PCIe4.0 Controller
- Fully compliant with PCI Express Base Specification Revision 4.0.
- Fully compliant with PIPE Specifications Revision 4.4.1.
- Support Root Complex and Endpoint Mode.
- Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps), Gen4 (16Gbps)
PCIe3.0 PHY
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
PCIe3.0 Controller
- Fully compliant with PCI Express Base Specification Revision 3.0.
- Fully compliant with PIPE Specifications Revision 4.4.1
- Support Root Complex and Endpoint Mode.
- Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps)