SAR ADC
Overview
Innosilicon SAR-ADC IP is a small-size, low power analog to digital converter. The converter is a charge-redistribution successive approximation ADC. It contains 4 input channels and outputs 10-bit conversion data.
Key Features
- Area: 0.135mm2 with IO and ESD
- Note: The area parameter is for reference only. Please refer to the final LEF file for the actual values.
- 10-bit resolution
- Up to 1MS/s sampling rate
- 4 single-ended input channels
- Current consumption: 1mA @ 1MS/s
- DNL<1LSB, INL<2LSB
Benefits
- Low power consumption
- Fully customizable
- Small area
- Simple integration process
Deliverables
- Databook and detailed physical implementation guides
- Complete set of timing models
- Library Exchange Format (LEF)
- Encrypted Verilog Models
- Layout vs. Schematic (LVS) report
- GDSII database
Technical Specifications
Foundry, Node
SMIC 55/40/28nm, UMC 40/28nm, TSMC 40/28/22/16/12/3nm, GF 55/28/22/14/12nm, Samsung 28/14nm, HLMC 40/28nm
GLOBALFOUNDRIES
In Production:
12nm
,
14nm
LPP
,
22nm
FDX
,
28nm
SLP
,
55nm
LPX
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 28nm SLP , 55nm LPX
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 28nm SLP , 55nm LPX
SMIC
In Production:
40nm
LL
,
55nm
LL
Silicon Proven: 14nm , 28nm HKC+
Silicon Proven: 14nm , 28nm HKC+
Samsung
In Production:
14nm
,
28nm
FDS
,
28nm
LPP
Silicon Proven: 14nm , 28nm FDS , 28nm LPP
Silicon Proven: 14nm , 28nm FDS , 28nm LPP
TSMC
In Production:
12nm
,
16nm
,
22nm
,
28nm
HPC
,
28nm
HPCP
,
28nm
HPM
,
40nm
G
,
40nm
LP
Silicon Proven: 3nm
Silicon Proven: 3nm
UMC
In Production:
28nm
Silicon Proven: 40nm LP
Silicon Proven: 40nm LP