MIPI C-PHY DSI RX IP

Overview

Innosilicon MIPI DSI RX IP implements the MIPI C-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communication protocols defined by MIPI® Alliance, which is intended for mobile system chip to chip communications. The MIPI DSI specification is specifically targeted for the display communications in image application processors.
Innosilicon MIPI DSI RX operates as a receiver of a DSI link, which consists of a MIPI C-PHY and a DSI controller.
? The MIPI C-PHY is used for the data transmission from a DSI compliant display module. In C-PHY, data streams are organized as packets. Error information is generated for the application layer to do further operation.
? The DSI controller works as a protocol layer between the application layer and physical layer, which aims to reconstruct the data streams from the C-PHY. Innosilicon DSI controller implements all three layers defined by DSI specification, including Pixel/Byte Packing, Low Level Protocol, and Lane Management.

Key Features

  • Compliant with MIPI® Alliance Specification for Display Serial Interface (DSI) V1.2
  • Compliant with MIPI® Alliance Specification for C-PHY V1.1
  • Compliant with MIPI® Alliance Specification for Display Command Set (DCS) V1.3
  • Compliant with AMBA 3.0 APB Specification
  • Data transfer rate ranging from 450Msps to 2.5Gsps per trio (C-PHY)
  • Supports Pixel Interface and Packet Interface
  • Supports data type: RGB/YCbCr (based on actual application scenarios)
  • Asynchronous transfer at low power mode with a bit rate of 10 Mbps on C-PHY
  • Supports HS, LP, ULPS modes
  • Bidirectional communication and escape mode support through data lane 0
  • Automatic termination control for HS and LP modes

Technical Specifications

Foundry, Node
SMIC 40nm
SMIC
In Production: 40nm LL
Silicon Proven: 40nm LL
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Semiconductor IP