LPDDR5X/5/4X/4 Combo PHY & Controller

Overview

Key Features

• LPDDR5 and LPDDR4/4X modes & signaling, rates from 20Mbps up to 8533Mbps (LPDDR5/5X) and 4266Mbps (LPDDR4/4X), respectively
• x16/x32/x64 data path interface extendable
• 1.05V/1.1V JEDEC IO standard, support 1.05V and 1.1V LVSTL I/Os
• support LPDDR4X 0.6V IO voltage and LPDDR5 0.5V/0.3V IO voltage
• Support LPDDR5 WCK mode, Data copy, Write X and Link ECC features
• Optional limited swing to VDDQ/3 in LPDDR4 mode
• Independent read and write timing adjustments with auto calibration
• Programmable write post-amble (0.5 tCK or 1.5 tCK)
• Support both PoP and discrete memory package
• Support various low power mode, support DFS and retention mode
• Support point to point memory sub systems and multi-rank
• PVT compensation and timing calibration for all corner reliability
• At speed BIST, scan insertion, PAD and internal loop back modes
• Various power-down modes for low power including self-refresh support
• Low jitter with superior noise rejection
• APB Port register access interface
• Implemented using 0.75V RVT&LVT core devices and 1.8V gate oxide IO devices
• Support both wire-bond and flip- chip packaging
• Wire-bond speed is package limited
• Support different DDRn type signal mapping for feasible PCB layout

Benefits

• Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market
• Zero risk with robust ESD architecture
• Maintains self-refresh I/O drive state during VDD power down
• Extensive EDA tool support for various design automation flows
• DFI4.0/4.1/5.0 compliant memory controller interface
• Takes full advantage of process power savings and speed capability
• Best in class low noise design to ensure best timing margin and signal integrity
• DFT functions to reduce test time and ensure high test coverage
• Several programmable PHY operating modes through simple register interface
• Per Bit De-skew to improve composite data eye during read cycles at high speed

Deliverables

• Verilog models
• LEF
• Place-and-route abstracts
• GDSII files
• LVS netlists
• Optional extracted HSPICE netlist for I/Os
• Data book, Application notes
• Silicon validation and ESD testing results
• Optional PCB reference design and Package Electrical Model
• Documentation: Documentation for the Innosilicon PHY will be delivered as part of the access package.

Technical Specifications