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LPDDR5 PHY IP

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Compare 82 LPDDR5 PHY IP from 11 vendors (1 - 10)
  • LPDDR4/4x/5/5x PHY
    • Supports JEDEC SDRAM standards including LPDDR4 (1.1V), LPDDR4x (0.6V), LPDDR5/5x (0.5V)
    • Supports data rates up to 4,266 Mbps LPDDR4/LPDDR5 and up to 8,533 Mbps LPDDR5x
    • Support for 16, 32 and 64-bit operation
    Block Diagram -- LPDDR4/4x/5/5x PHY
  • LPDDR5 IP solution
    • Support LPDDR5 up to 6400Mbps
    • Support Channel equalization with 1-tap DFE
    • Support single-ended mode on CK, WCK and read DQS below 3200Mbps
    • Support Link ECC for RDQS and DM
    Block Diagram -- LPDDR5 IP solution
  • LPDDR5X Synthesizable Transactor
    • Supports 100% of LPDDR5X protocol draft JEDEC specification and JESD209-5B specification.
    • Supports all the LPDDR5X commands as per the specs.
    • Supports device density up to 32GB.
    • Supports X8 and X16 device modes.
    Block Diagram -- LPDDR5X Synthesizable Transactor
  • LPDDR5 Synthesizable Transactor
    • Supports 100% of LPDDR5 protocol standard JESD209-5, JESD209-5A and JESD209-5B.
    • Supports all the LPDDR5 commands as per the specs
    • Supports device density up to 32GB
    • Supports X8 and X16 device modes
    Block Diagram -- LPDDR5 Synthesizable Transactor
  • LPDDR5 DFI Synthesizable Transactor
    • Compliant with DFI version 5.0 Specifications.
    • Supports LPDDR5 devices compliant with JEDEC LPDDR5 SDRAM Standard JESD209-5.pdf, JESD209-5A and LPDDR5X (Draft).
    • Supports for Read data bus inversion.
    • Supports for Write data bus inversion.
    Block Diagram -- LPDDR5 DFI Synthesizable Transactor
  • LPDDR5X PHY
    • Compatible with JEDEC standards LPDDR4X , LPDDR5 and LPDDR5X SDRAMs
    • Supports for data transfer rate up to 8533Mbps
    • DFI 5.0 for PHY and controller interfaces
    • Supports both firmware-based training and hardware-based training
    Block Diagram -- LPDDR5X PHY
  • LPDDR5/4/4X PHY - TSMC N7 for Automotive, ASIL B Random, AEC-Q100 Grade 2
    • Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
    • Support for data rates up to 6400 Mbps
    • Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5/4/4X PHY - TSMC N7 for Automotive, ASIL B Random, AEC-Q100 Grade 2
  • LPDDR5/4/4X PHY - TSMC N7
    • Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
    • Support for data rates up to 6400 Mbps
    • Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5/4/4X PHY - TSMC N7
  • LPDDR5/4/4X PHY - TSMC N6
    • Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
    • Support for data rates up to 6400 Mbps
    • Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5/4/4X PHY - TSMC N6
  • LPDDR5/4/4X PHY - TSMC N5
    • Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
    • Support for data rates up to 6400 Mbps
    • Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5/4/4X PHY - TSMC N5
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