NeuroMatrix® Core 3 (NMC3) is a high performance DSP core with VLIW/SIMD/decoupled architectures. The core includes a 32-bit RISC processor and a 64-bit VECTOR co-processor to support vector operations with elements of variable bit length. The NMC3 core has been silicon proven. It has scalable performance and original instruction set.
High performance DSP core with VLIW/SIMD/decoupled architectures
Overview
Key Features
- 32/64-bit RISC Core
- 3 scalar instructions per clock cycle (ALU operation, address modification and memory read/write operation)
- 64-bit Vector Coprocessor (fixed point):
- Programmable data length from 2 to 64 bits packed to 64 bit data words
- Basic operation is matrix by matrix multiplication
- Two saturation operations execution per clock cycle
- Performance (MAC - Multiplication and Accumulation per clock cycle) -
- 2 MAC for 32-bit data
- 4 MAC for 16-bit data
- 24 MAC for 8-bit data
- 80 MAC for 4-bit data
- 224 MAC for 2-bit data
- 1K*64 bit Instruction Cache
- Up to 4 External Address Generators
- Up to 4 Internal Memory Banks Support
- AXI 3.0 External Memory Interface
- Up to 32 External/internal Interrupts Support
- Two 32-bit Timers
- DMA controller
Applications
- Hydro- and radiolocation
- IR and video processing
- Artificial Neural net emulation
- Navigation
- CDMA - TDMA base stations
- Vector and matrix computations
Technical Specifications
Maturity
Silicon
Availability
Available now
Related IPs
- High performance dual-issue, out-of-order, 7-stage Vector processor (DSP) IP
- Ultra High Performance AES-XTS/ECB Core
- Ultra High Performance AES-GCM/CTR Core
- High Performance AES-XTS/ECB Core
- ARC HS45D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions for embedded applications
- ARC HS47D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions and I&D cache