DDR4/LPDDR4X/4 Combo PHY & Controller

Overview

The INNOSILICON DDR IPTM Mixed-Signal LPDDR4/4X/DDR4 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports all JEDEC LPDDR4/4X/DDR4 SDRAM components in the market. The PHY components contain DDR specialized functional and utility SSTL I/Os, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. DDRn bus width can be from 4 bit to 72 bit or more. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.
The combo PHY solution includes DDRn controller and PHY. With configurable timing and driving strength parameters to interface to the wide variety of SDRAMs, the PHY is very flexible with advanced command capability to increase SDRAM operation efficiency.

Key Features

DDR4 and LPDDR4/4X/3 modes & signaling, rates from 20Mbps up to 3200Mbps (DDR4), 3733Mbps (LPDDR4/4X), respectively
x16/x32/x64 data path interface extendable
1.2V/1.1V JEDEC IO standard, support 1.2V POD_12 I/Os and 1.1V LVSTL I/Os
Optional limited swing to VDDQ/3 in LPDDR4 mode
Independent read and write timing adjustments with auto calibration
Programmable write post-amble (0.5 tCK or 1.5 tCK)
Support 0.6V VDDQL LPDDR4x IO operating mode
Supports point to point memory sub systems and multi-rank
PVT compensation and timing calibration for all corner reliability
At speed BIST, scan insertion, PAD and internal loopback modes
Various power-down modes for low power including self-refresh support
Low jitter with superior noise rejection
APB Port register access interface
Implemented using 0.8V RVT&LVT core devices and 1.8V gate oxide IO devices
Supports both wire-bond and flip- chip packaging
Support different DDRn type signal mapping for feasible PCB layout

Benefits

Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market,
Zero risk with robust ESD architecture
Maintains self-refresh I/O drive state during VDD power down
Extensive EDA tool support for various design automation flows
Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
DFI3.1 compliant memory controller interface
Flexible pad ring configuration to adapt for various design and chip scenarios
Integration with other INNOSILICON interface IP
Takes full advantage of process power savings and speed capability
Best in class low noise design to ensure best timing margin and signal integrity
DFT functions to reduce test time and ensure high test coverage
Several programmable PHY operating modes through simple register interface
Per Bit De-skew to improve composite data eye during read cycles at high speed

Deliverables

Verilog models
LEF
Place-and-route abstracts
GDSII files
LVS netlists
Optional extracted HSPICE netlist for I/Os
Data book, Application notes
Silicon validation and ESD testing results
Optional PCB reference design and Package Electrical Model
Documentation: Documentation for the Innosilicon PHY will be delivered as part of the access package.

Technical Specifications

Foundry, Node

TSMC16/12nm, SMIC14/12nm, Samsung 11nm

Maturity

Silicon Proven

Availability

Available

SMIC

In Production: 14nm
Silicon Proven: 14nm

Samsung

In Production: 11nm
Silicon Proven: 11nm

TSMC

In Production: 12nm , 16nm
Silicon Proven: 12nm , 16nm

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