DDR4/3/LPDDR4X/4/3 Combo PHY & Controller

Overview

Key Features

• DDR4/3 and LPDDR4/4X/3 modes & signaling, rates from 20Mbps up to 2667Mbps (DDR4/LPDDR4/4X) and 2133Mbps (DDR3/LPDDR3), respectively
• x16/x32 data path interface extendable
• 1.2V/1.1V/1.5V JEDEC IO standard, support 1.5V SSTL, 1.2V POD_12 I/Os and 1.1V LVSTL I/Os
• Optional limited swing to VDDQ/3 in LPDDR4 mode
• Independent read and write timing adjustments with auto calibration
• Programmable write post-amble (0.5 tCK or 1.5 tCK)
• Support 0.6V VDDQL LPDDR4x IO operating mode
• Supports point to point memory sub systems and multi-rank
• PVT compensation and timing calibration for all corner reliability
• At speed BIST, scan insertion, PAD and internal loopback modes
• Various power-down modes for low power including self-refresh support
• Low jitter with superior noise rejection
• APB Port register access interface
• Implemented using 1.0V RVT&LVT core devices and 1.8V gate oxide IO devices
• Supports both wire-bond and flip- chip packaging
• Support different DDRn type signal mapping for feasible PCB layout

Benefits

• Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market,
• Zero risk with robust ESD architecture
• Maintains self-refresh I/O drive state during VDD power down
• Extensive EDA tool support for various design automation flows
• Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
• DFI3.1 compliant memory controller interface
• Flexible pad ring configuration to adapt for various design and chip scenarios
• Integration with other INNOSILICON interface IP
• Takes full advantage of process power savings and speed capability
• Best in class low noise design to ensure best timing margin and signal integrity
• DFT functions to reduce test time and ensure high test coverage
• Several programmable PHY operating modes through simple register interface
• Per Bit De-skew to improve composite data eye during read cycles at high speed

Deliverables

• Verilog models
• LEF
• Place-and-route abstracts
• GDSII files
• LVS netlists
• Optional extracted HSPICE netlist for I/Os
• Data book, Application notes
• Silicon validation and ESD testing results
• Optional PCB reference design and Package Electrical Model
• Documentation: Documentation for the Innosilicon PHY will be delivered as part of the access package.

Technical Specifications