DVB IP Core

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Compare 81 DVB IP Core from 21 vendors (1 - 10)
  • DVB-C Demodulator
    • DVB-C EN 300 429 & ITU-T J.83 Annex A & Annex C compliant QAM demodulator
    • Supports IF input
    • QAM constellations 16, 32, 64, 128 and 256
    • Symbol rates up to 7 MBaud
    Block Diagram -- DVB-C Demodulator
  • DVB-RCS2 Multi-Carrier Receiver
    • Compliant with ETSI EN 301 545-2 (DVB-RCS2)
    • Support for Linear Modulation Bursts of Table A-1
    • Optional support for Spread-spectrum
    Block Diagram -- DVB-RCS2 Multi-Carrier Receiver
  • DVB-S2X Demodulator
    • Compliant with DVB-S2X
    • Supports CCM, ACM and VCM modes
    • Support for QPSK up to 256-APSK
    Block Diagram -- DVB-S2X Demodulator
  • ISO/IEC 21122-1 JPEG-XS Standard Codec
    • Support YUV444/ YUV422 input format
    • Support color depth: 8bit / 10bit(optional) /12 bit(optional).
    • Multi-Channel (optional)
    • Visual Lossless compression
    Block Diagram -- ISO/IEC 21122-1  JPEG-XS Standard Codec
  • DVB-S2/S/T2/T/C Combo Demodulator IP (Silicon Proven)
    • Combines a configurable DVB-T2/T/C/S/S2 demodulator.
    • AGC derived from IF
    • Low-power process, design and architecture
    • Includes full suite of low-level drivers and application software, detailed user manuals and reference design schematics
    Block Diagram -- DVB-S2/S/T2/T/C Combo Demodulator IP (Silicon Proven)
  • DVB-C Demodulator IP (Silicon Proven)
    • QAM and FEC solution
    • ITU-T J.83 Annexes A/B/C, DVB-C specification (ETSI 300 429)
    • Nordig Unified v2.4 and SARFT compliant
    • Up to 7.2 Ms/s symbol rate
    Block Diagram -- DVB-C Demodulator IP (Silicon Proven)
  • DVB-T2/T Demodulator and Decoder IP (Silicon Proven)
    • DVB-T2 with T2-base profile of ETSI EN- 302755 v1.3.1,DTG7 v3 and Nordig Unified v2.4 compliant, 1.7-5-6-7 and 8 MHz normal and extended BW signals supported, GS streams, FEF and MISO supported
    • DVB-T demodulator: Compliant with ETSI EN-300744 v1.5.1, DTG7 v3 and Nordig Unified v2.4 compliant, 6-7 and 8 MHz BW supported
    • DVB-T/T2 compatible with zero-high- and legacy-IF tuners (CAN or silicon)
    • Embedded microcontroller (DVB-T2 task sequencing by firmware and monitoring)
    Block Diagram -- DVB-T2/T Demodulator and Decoder IP (Silicon Proven)
  • DVB-S2/DVB-S2X Demapper/LDPC/BCH Decoder
    • Digital Video Broadcasting Second Generation (DVB-S2) and Extensions (DVB-S2X) compatible
    • Nominal code rates from 1/5 to 9/10
    Block Diagram -- DVB-S2/DVB-S2X Demapper/LDPC/BCH Decoder
  • DVB-S2/S Demodulator and Decoder IP (Silicon Proven)
    • Compatible with all ACM (Adaptive Coding and Modulation), VCM (Variable Coding and Modulation) and CCM (Constant Coding and Modulation) configurations of ETSI EN 302 307-1 and ETSI EN 302 307-2.
    • Frame-by-frame selection of frame size, FEC code rate and modulation format (QPSK, 8PSK, 16APSK and 32APSK).
    • Support for DVB-S2 extensions (S2X) FEC code-rates and modulation formats (64APSK, 128APSK and 256APSK)
    • Support for an arbitrary range of symbol rates up to 40% of the master clock frequency
    Block Diagram -- DVB-S2/S Demodulator and Decoder IP (Silicon Proven)
  • Digital PreDistortion IP
    • Better than 40 dB ACLR improvement depending upon the DPD configuration and system specifications/characteristics.
    • Scalable linearization capabilities to suit deployment system and optimise silicon resources.
    • Provides quadrature error correction (QEC), automatic gain control and frequency error compensation.
    • Supports single or multi-carrier instantaneous signal bandwidths from kHz to hundreds of MHz.
    Block Diagram -- Digital PreDistortion IP
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