Bunch of Wires IP
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Bunch of Wires (BoW) is an energy-efficient, easy-to-use PHY interface between a pair of die inside a single package. The BoW PHY is defined as a single unidirectional slice. Multiple slices are combined to create links of the desired throughput. A link may be symmetric, asymmetric or unidirectional. The BoW PHYs between two die are physically connected through wires on a substrate or interposer.
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Bunch of Wires IP
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8
Bunch of Wires IP
from 6 vendors
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8)
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2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- High Bandwidth Density and Data Rates
- Package Configurability
- Energy Efficiency
- Fully Integrated Solution
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BoW Verification IP
- Support AXI5-Lite D-64 Interface Profile
- Support AXI5-Lite D-32 Interface Profile
- Support PIPE interface PHY to upper layers(System Interface)
- Support LPIF interface PHY to upper layers(System Interface)
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UCIe and BOW Universal PHY
- Novel Redundancy for Hi-Rel,
- Support for 16&18-bit wide data,
- Support Synchronous Operation,
- Supports Advanced packaging,
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Die-to-Die PHY
- 64 data lanes with configuration and bump map layout dependent on the PHY type (UCIe, BoW, UMI, SBD)
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Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications
- High data rate of 2–24 Gb/s
- Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
- Very low latency of < 2 ns PHY-to-PHY
- Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
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2GBps Low Power D2D Interface
- Core Device: 0.9V
- I/O Device: 1.8V Standard
- Core: Uses SVT only
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2Gbps Low Power D2D Interface
- Core Device: 0.8V
- I/O Device: 1.8V Standard
- Core: Uses SVT only
- BEOL: M8 and below
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600Mbps Low Power D2D Interface in 16nm
- Core Device: 0.8V
- I/O Device: 1.8V Standard
- Core: Uses SVT only