Memory Controller & PHY IP for TSMC
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Memory Controller & PHY IP
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25
Memory Controller & PHY IP
for TSMC
from 7 vendors
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10)
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
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Secure Digital I/O offerings
- Secure Digital
- Physical Features
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1.8V/3.3V Switchable GPIO With 5V I2C Open Drain & Analog in 16/12nm
- Multi-voltage 1.8V / 3.3V switchable operation
- 4 selectable drive strengths (25-235MHz @1.8V, 10pF)
- Full-speed output enable
- Independent power sequencing
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ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
- Support ONFi 4.0 IO Electrical Specification
- Support Legacy up to 50MHz
- Support NV-DDR2 with operating frequency up to 533Mbps
- Support NV-DDR3 with operating frequency up to 800Mbps
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ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
- Support ONFi 4.1 IO Electrical Specification
- Support Legacy up to 50MHz
- Support NV-DDR2 up to 533Mbps
- Support NV-DDR3 up to 1200Mbps
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TSMC 3nm (N3E) 1.8V SD/eMMC PHY
- Completely hardened PHY solution along with programmable delay chains & I/Os
- Fully selectable output impedance
- Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
- Automotive G1/G2 supported, ASIL-B certified
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SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6)
- Compliant with eMMC5.1 and SD 6.0
- Supports 1.2/1.8V and 3.3V bus voltages and all the operating modes for SD 6.0 and eMMC5.1
- Supports 1.8V signaling for SD 6.0 host–low voltage signaling (LVS)
- Includes high speed IOs and DLL/delay lines to guarantee alignment between the application processor and memory device
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SD 4.1 UHS-II PHY for TSMC 12nm FF
- Compliant to SD Specifications Part 1 UHS-II Specification Volume 2: PHY* and SD Specifications Part 1 UHS II Specification Volume 1: System and Protocol”