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DDR IP for TSMC

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Compare 12 DDR IP for TSMC from 2 vendors (1 - 10)
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  • 3nm
  • LPDDR5X/5/4X PHY - TSMC N3P
    • Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
    • Support for data rates up to 8533 Mbps
    • Designed for rapid integration with Synopsys LPDDR5X/5/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5X/5/4X PHY - TSMC N3P
  • LPDDR5X/5/4X PHY - TSMC N3E
    • Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
    • Support for data rates up to 8533 Mbps
    • Designed for rapid integration with Synopsys LPDDR5X/5/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5X/5/4X PHY - TSMC N3E
  • LPDDR5X/5/4X PHY - TSMC N3A for Automotive, ASIL B Random, AEC-Q100 Grade 2
    • Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
    • Support for data rates up to 8533 Mbps
    • Designed for rapid integration with Synopsys LPDDR5X/5/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5X/5/4X PHY - TSMC N3A for Automotive, ASIL B Random, AEC-Q100 Grade 2
  • DDR5 PHY - TSMC N3P
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5 PHY - TSMC N3P
  • DDR5 MRDIMM2 PHY - TSMC N3P
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5 MRDIMM2 PHY - TSMC N3P
  • DDR5 PHY - TSMC N3E
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5 PHY - TSMC N3E
  • LPDDR5X/5/4X PHY in TSMC (N5, N4P, N3E)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps
    • DFI 5.0 compliant interface to the memory controller
    • DFI Frequency Ratio Support: DFI 1:1:4, 1:1:2 modes (DFICLK:CK:WCK)
  • HBM3 PHY V2 in TSMC (N5, N3E)
    • Low latency, small area, low power
    • Compatible with JEDEC standard HBM3 DRAMs
    • Data rates up to 9600 Mbps
    • 8H, 12H and 16H HBM3 DRAM stacks supported
  • HBM3 PHY V2 (Hard 1) in TSMC (N3E)
    • Low latency, small area, low power
    • Compatible with JEDEC standard HBM3 DRAMs
    • Data rates up to 9600 Mbps
    • 8H, 12H and 16H HBM3 DRAM stacks supported
  • DDR5 PHY in TSMC (N3E, N5)
    • Low latency, small area, low power
    • Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3200 Mbps
    • DFI 5.0 compliant interface to the memory controller
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