Ultra-Low Phase Noise Delta Sigma Fractional-N LC PLL
Overview
Fractional-N delta sigma LC based frequency synthesizer intended for RF LO synthesis or high performance clock generation applications.
Key Features
- Fully integrated 8.25GHz CMOS LC PLL (5.28GHz version also available)
- 10MHz - 40MHz input range
- 7GHz -- 8.25GHz output frequency range
- widepy programmable output divider allows outputs at any frequency from 117MHz to >1GHz
- 24 bit fractional resolution
- 3rd order noise shaping eliminates fractional spurs
- Long Term Jitter <150fs RMS (integrated 1MHz -- 1GHz)
- Reference spur better than -54dBc @ 8.25GHz
Benefits
- #NAME?
Deliverables
- GDSII
- CDL Netlist (MG Calibre Compatible)
- Functional Verilog Model
- Liberty timing module (.lib)
- LEF
- Application Note
Technical Specifications
Foundry, Node
TSMC 28HPM, HPC, HPC+
Maturity
Pre-silicon
Availability
Available Now
TSMC
In Production:
28nm
HPCP
,
28nm
HPM
Pre-Silicon: 28nm HP
Silicon Proven: 28nm , 28nm HP , 28nm HPC , 28nm HPCP , 28nm HPL , 28nm HPM , 28nm LP
Pre-Silicon: 28nm HP
Silicon Proven: 28nm , 28nm HP , 28nm HPC , 28nm HPCP , 28nm HPL , 28nm HPM , 28nm LP
UMC
Silicon Proven:
28nm
HPC
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