Ultra-low Jitter Fractional-N Frequency Synthesizer PLL (5nm - 180nm)

Overview

Key Features

• Jitter-Power optimized to meet PCIe1-5 reference clock requirements
• Wide functional range
• 24 bit fractional resolution so output frequency is programmable in steps less than 0.01ppm
• Noise Cancellation DAC enables ultra-low jitter in fractional mode -- better than "Low jitter" integer PLLs from many others
• Pairs with DPLL digital loop filter to construst a Jitter Cleaner PLL
• Small footprint
• Optional Spread Spectrum clock generation capability

Benefits

• Jitter-Power optimized to meet PCIe1-5 reference clock requirements - replaces 300mW/$2.50 clock chip
• Low area on chip -- keepouts = DRC limit in most cases
• Self biased and automatically adjusts for any input frequency, so no complicated programming is required

Block Diagram

Applications

• SerDes reference clock
• AFE/ADC/DAC reference clock

Deliverables

• GDSII
• CDL Netlist (MG Calibre Compatible)
• Functional Verilog Model
• Liberty timing models (.lib)
• LEF
• Application Note

Technical Specifications