Ultra-Low Phase Noise Digital LC PLL

Overview

Key Features

• Wideband integrated jitter <400fs in integer mode, <800fs in fractional mode with high-speed / clean reference with active fractional noise cancellation
• Passes PCIe6 reference clock requirements with wide margin
• Reference spur <200fs RMS
• Random period jitter <30fs RMS
• Low-leakage standby mode for fast re-locking
• “Instant” frequency lock from standby
• < 0.1% frequency error over PVT for open-loop DCO
• ±8% frequency tuning range
• Programmable loop bandwidth
• Low power (<10mW)
• Small (<0.1mm2)

Benefits

• Ultra-low phase noise allows PLL to be used for almost any high performance clocking application common in modern electronics
• Fully integrated so no external components are required
• Wide tuning range allows a single IP macro to be used for multiple applications
• Built-in frequency calibration enable high yield in mass production and ensures the frequency is always correct regardless of process or temperature variations

Block Diagram

Deliverables

• GDSII
• CDL Netlist (MG Calibre Compatible)
• Functional Verilog Model
• Liberty timing module (.lib)
• LEF
• Application Note

Technical Specifications