SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)

Overview

The Digital Blocks DB-SPI-S-AMBA-BRIDGE is a Serial Port Interface (SPI) Controller Verilog IP Core supporting SPI Slave Interface to APB Master Bus. The DB-SPI-S-AMBA-BRIDGE performs a SPI2APB function, allowing incoming SPI Receive transactions to write or read data to/from an AMBA APB Bus

Key Features

  • Slave SPI Modes
  • Three release configurations:
    • SPI Slave to/from APB Master (SPI2APB)
    • SPI Slave to/from AXI Master SPI (AXI)
    • SPI Slave to/from AHB5 Master (SPI2AHB5)
  • Configurable SPI Modes:
    • Standard SPI Mode (1 Data Lane)
    • Dual SPI Mode (2 Data lanes)
    • Quad SPI Mode (4 Data Lanes)
  • Programmable SPI Frame Formats:
    • Programmable LSB-first or MSB-first frames
  • APB Bus Interface performance
    • Separate Transmit / Receive FIFOs
  • Available AMBA Microprocessor Interfaces:
    • AXI / AHB / APB Buses
    • 32 bit Data Interface
  • Compliance with ARM AMBA and Freescale / Motorola SPI specifications:
  • Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.

Deliverables

  • Verilog or VHDL RTL Source or technology-specific netlist.
  • Comprehensive testbench suite with expected results.
  • Synthesis scripts.
  • Installation & Implementation Guide.
  • Technical Reference Manual.

Technical Specifications

Foundry, Node
Chartered, IBM, LSI. OKI, Silterra, SMIC, STMicroelectronics, Tower, TMSC, UMC
Maturity
Successful in Customer Implementations
Availability
Immediately
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Semiconductor IP