I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)

Overview

The Digital Blocks DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AHB system Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master / slave controller and one or more master / slave devices on the I2C Bus. The companion products, the DB-I2C-MS-APB, DB-I2C-MS-AXI, DB-I2C-MS-AVLN, DB-I2C-MS-AXI-Lite, support on-chip bus interfaces with microprocessors such as the ARM, MIPS, PowerPC, and ARC.

Digital Blocks offers I2C Controller Master/Slave, Master only, and Slave only IP with AXI / AHB / APB / Avalon / Qsys Interfaces. In addition, besides interfacing to a CPU, the I2C Controllers can transfer blocks of data directly between System Memory or Registers and the I2C Bus.

Key Features

  • I2C Master / Slave with Parameterized FIFO:
    • Targets embedded processors with high performance algorithm requirements, by independently controlling the Transmit or Receive of bytes of information:
      • For Transmits, the processor writes the Slave Address & bytes of information into the FIFO, sets a start control bit, and waits for an interrupt or polls a status bit signaling completion
      • For Receive, the processor writes the Slave Address into the DB-I2C-MS-AHB, enables the controller, and waits for an interrupt or polls a status bit signaling completion. The processor then reads the bytes of information from the FIFO.
    • Small VLSI footprint
    • Master Controller Modes:
      • Master – Transmitter
      • Master – Receiver
    • Slave Controller Modes:
      • Slaver – Transmitter
      • Slave – Receiver
    • Multi-Master, Clock Synchronization, Arbitration, SCL held low by Slave, & Repeated Start capabilites
    • Parameterized FIFO depth for higher performance. Optional 16 or 32-bit processor interface
    • Supports three I2C bus speeds:
      • Standard mode (100 Kb/s)
      • Fast mode (400 Kb/s)
      • Fast mode plus (1 Mbit/s)
    • 8 sources of internal interrupts with masking control
    • Compliance with AMBA AXI and I2C specifications:
      • AMBA AHB Protocol Specification (V2.0)
      • Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000 and NXP Rev 0.3 19 June 2007
    • Fully-synchronous, synthesizable Verilog or VHDL RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.

    Benefits

    • The DB-I2C-MS-AHB Controller IP Core targets embedded processor applications with high performance algorithm requirements. While most I2C controllers require high processor interaction involvement, the DB-I2C-MS-AHB contains a parameterized FIFO and Finite State Machine Control for the processor to off-load the I2C transfer to the DB-I2C-MS-AHB Controller. Thus, while the DB-I2C-MS-AHB is busy, independently controlling the I2C Transmit or Receive transaction of data, the processor can go off and complete other tasks.

    Deliverables

    • Verilog or VHDL RTL Source or technology-specific netlist.
    • Comprehensive testbench suite with expected results.
    • Synthesis scripts.
    • Installation & Implementation Guide.
    • Technical Reference Manual.

    Technical Specifications

    Foundry, Node
    Chartered, IBM, LSI. OKI, Silterra, SMIC, STMicroelectronics, Tower, TMSC, UMC
    Maturity
    Successful in Customer Implementations
    Availability
    Immediately
    GLOBALFOUNDRIES
    Pre-Silicon: 28nm HPP , 32nm , 55nm
    Silicon Proven: 28nm HPP
    LFoundry
    Pre-Silicon: 150nm
    Renesas
    Pre-Silicon: 40nm , 90nm
    SMIC
    Pre-Silicon: 40nm LL
    Silicon Proven: 55nm G
    Silterra
    Pre-Silicon: 90nm
    Silicon Proven: 130nm
    TSMC
    In Production: 45nm LP
    Pre-Silicon: 28nm LP , 40nm G , 45nm LP , 55nm LP , 65nm GP , 90nm GOD
    Silicon Proven: 40nm G , 55nm GP , 65nm LP
    Tower
    Pre-Silicon: 130nm
    Silicon Proven: 180nm
    UMC
    In Production: 55nm
    Pre-Silicon: 40nm LP
    Silicon Proven: 40nm LP
×
Semiconductor IP