MIPI D-PHY DSI TX+ (Transmitter) IP in Samsung 28FDSOI

Overview

The MXL-DPHY-DSI-TX+ is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.1, which is backward compatible with MIPI Specification for D-PHY v1.2. and D-PHY v1.1. The PHY is configured as a MIPI master supporting Display Serial interface DSI. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.

Key Features

Supports MIPI Specification for D-PHY Version 2.1
Consists of 1 Clock lane and 4 Data lanes
Supports both high speed and low-power modes
80 Mbps to 1.5 Gbps data rate in high speed mode
10 Mbps data rate in low-power mode
Low power dissipation
Testability support

Benefits

The TX+ is a Mixel proprietary configuration that is optimized to support full-speed production and in-system testing while minimizing area and leakage power.

Block Diagram

Applications

Mobile
Displays
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

Samsung 28nm FDSOI

Maturity

Silicon Proven

Availability

Now

Request Info