MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+

Overview

The MXL-DPHY-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5.
The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications.

Key Features

  • Supports MIPI Alliance Specification for D-PHY Version 2.5
  • Consists of 1 Clock lane and 2 Data lanes
  • Embedded, high performance, and highly programmable PLL
  • Supports both low-power mode and high speed mode with integrated SERDES
  • 80 Mbps to 1.5 Gbps data rate per lane without skew calibration in D-PHY mode
  • 2.5 Gbps data rate per lane with skew calibration in high speed D-PHY mode
  • 10 Mbps data rate in low-power mode
  • Low power dissipation
  • Testability support

Benefits

  • This IP supports automotive applications and is AEC-Q100 Automotive Grade 2 ready and ISO 26262 ASIL-B ready.

Block Diagram

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+ Block Diagram

Applications

  • Mobile
  • Cameras/Sensors
  • IoT
  • VR/AR/MR
  • Consumer electronics
  • Automotive

Deliverables

  • Specifications
  • GDSII
  • LVS netlist
  • LEF file
  • IBIS Model
  • Verilog Model
  • Timing Model
  • Integration Guidelines
  • RTL
  • Documentation
  • One year support

Technical Specifications

Foundry, Node
TSMC, 28HPC+
Maturity
Available Upon Request
Availability
Available Upon Request
×
Semiconductor IP