Low-jitter Ring PLL

Overview

Integer PLL combines low area with wide range and very low jitter for clocking AFEs and providing reference sources for High-speed serial links

Widely Programmable Integer PLL is a multi-function, general purpose frequency synthesizer. The design is optimized to provide ultra-low jitter making this PLL suitable for clocking fast AFEs and high-end SerDes circuits. Ultra-wide input and output ranges along with best-in-class jitter
performance allow the PLL to be used for almost any clocking application. With excellent supply noise immunity, the PLL is ideal for use in noisy mixed signal SoC environments.

Key Features

10MHz up to 640MHz input frequency range (65G)
14MHz up to 2.8GHz output frequency range (65G)
Small footprint (0.02mm^2 in 65G
Integrated Long Term Jitter typically 1ps RMS -- meets requirements for PCIe gen 1, 2, 3 and SATA 1, 2, 3 reference clock
Phase Noise better than –120dBc/Hz @ 100kHz offset
Reference Spurs better than –65dBc
Differential output simplifies output routing
Separate supply domains for optimal jitter isolation in noisy SoC environments
Wide range analog supply range (2.25V to 3.63V in 65G)
Simple digital control interface

Benefits

No external components required
No additional supply decoupling required

Deliverables

GDSII
CDL Netlist (MG Calibre Compatible)
Functional Verilog Model
Liberty timing models (.lib)
LEF
Application Note

Technical Specifications

Foundry, Node

TSMC 28nm - 180nm; Global Foundries 28nm - 65nm; SMIC 65nm - 130nm; IBM 65nm - 180nm; ST 90nm

Maturity

Mass Production

Availability

Available Now

GLOBALFOUNDRIES

In Production: 65nm LPe
Pre-Silicon: 55nm

SMIC

Pre-Silicon: 28nm HK , 28nm PS , 65nm LL , 130nm G
Silicon Proven: 55nm LL

TSMC

In Production: 65nm GP
Pre-Silicon: 65nm LP

UMC

Pre-Silicon: 65nm SP
Silicon Proven: 55nm

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