Controller IP for the MIPI I3C interface
The Cadence® IP Family for MIPI® Protocols delivers area-optimized interface IP with the low power and high performance required for today's leading-edge devices. One member of this family is the Cadence Initiator Controller IP for MIPI I3CSM. Compliant with the latest MIPI I3C specification and legacy compatible with I2CSM, the Controller IP is engineered to quickly and easily integrate into any mobile embedded system-on-chip (SoC) device and expand sensor communication capabilities with better power efficiency. Developed by experienced teams with industry-leading domain expertise, verified by silicon-proven and mature I2C IP and validated on a FPGA platform to reduce risk for designers, the IP will connect seamlessly to the Controller IP. The Controller IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, system, and peripheral IP.
I3C Controller
Overview
Key Features
- Support for multiple transmission modes: Single Data Rate (SDR) and High Data Rate (HDR)
- Compliant with the latest I3C specification
- Support for I3C common command codes
- Support for Full, Reduced, and Simplified data ports
- Dynamic address assignment (DAA) support
- Support for in-band interrupts, hot-join, peer-to-peer request, current initiator control request
- f I2C legacy device support
- Arm® AMBA® APB interface support for register access
- Command queue support
Applications
- Automotive,
- Communications,
- Consumer Electronics,
- Data Processing,
- Industrial and Medical,
- Military/Civil Aerospace,
- Others
Deliverables
- Documentation—Integration guide, user guide, and release notes
- Clean, readable, synthesize-able Verilog RTL
- Synthesis scripts
- Sample verification testbench with integrated BFM, monitors, and sanity tests
Technical Specifications
Maturity
Silicon Proven