Comcores Ethernet Switch 10G IP core is a highly configurable and size optimized implementation of a non-blocking switch that allows continuous transmissions between 10G Ethernet ports. The switch supports MAC learning, VLAN 802.1Q, and multicast. Each port provides a native interface for XGMII Ethernet PHY devices.
Ethernet Switch 10G
Overview
Key Features
- Feature-rich
- Automatic MAC addresses learning and aging
- Support programmable static forwarding entries
- Full duplex Ethernet interfaces
- Supports VLAN
- Easy to use
- XGMII interfaces for attaching external Physical Layer devices (PHY)
- Easy integration with standard Xilinx AXI4 Lite control interface
- Can be used in managed or unmanaged implementations
- Highly Configurable
- Up to 16 ports configurable at compile time
- Configurable scheduling behavior (round-robin, fair queuing)
- Support Ethernet Multicast
- Silicon Agnostic
- Designed in VHDL and targeting both ASICs and FPGAs
Benefits
- Architecture supports a large number of ports
- Large number of features supported default
- Ultra-compact size
- Silicon Agnostic
- Customization can be provided
Block Diagram
Deliverables
- The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note
- Simulation Environment, including Simple Testbed, Test case, Test Script
- Access to support system and direct support from Comcores Engineers
- Synopsys Lint and CDC
Technical Specifications
Maturity
Mature
Availability
Avaliable