DisplayPort IP
Welcome to the ultimate DisplayPort IP hub! Explore our vast directory of DisplayPort IP cores.
DisplayPort IP Cores are designed for transmission and reception of serial-digital video for consumer and professional displays. These IP cores help users to implement a DisplayPort video interface as defined by VESA DisplayPort specifications.
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DisplayPort IP
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81
DisplayPort IP
from 20 vendors
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10)
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VESA DisplayPort 2.0 FEC RX
- VESA DisplayPort 2.0 compliant
- Reed Solomon RS (198,194) FEC, 8-bit symbols
- Multiple symbols per clock
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VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC)
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VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- VESA DisplayPort 1.4 compliant
- Reed-Solomon (254,250) FEC, 10-bit symbols
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VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
- VESA DisplayPort 1.4 compliant
- Reed-Solomon (254,250) FEC, 10-bit symbols
- Two-way interleaving for 1-, 2-, and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
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Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
- eDP version 1.4a / DP version 1.4 compliant transmitter
- Supports HDCP1.4 and HDCP2.2(Optional)
- Supports Forward Error Correction (Optional)
- Consists of configurable (4/2/1) link channels and one AUX channel
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eDP1.4/DP1.3 TX Link IP
- eDP version 1.4a, DP version 1.3 compliant receiver
- Supports HDCP Decryption
- Supports both 1.62/8.1Gbps data rate
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Intra-Panel Low-Power TX 28nm
- COG and COF transmitter
- Data Rate : 120M ~ 3.2Gbps
- Power Down Mode
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DisplayPort Receiver Link Controller
- Silicon proven on multiple ASIC and FPGA processes
- Capable of operating without a host CPU in low complexity applications
- Horizontal and vertical video delimiter signals with 1, 2 or 4 pixels per output cycle, supporting up to 16K resolution output; deep color and HDR support
- 1.62 to 8.1 Gbps link rate across 1, 2, or 4 lanes
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DisplayPort Transmitter Link Controller
- Silicon proven on multiple ASIC and FPGA processes with multiple PHY partners.
- 1, 2 or 4 pixels per input cycle, supporting up to 16K resolution input per source
- 1.62-8.1Gbps link rate across 1,2, or 4 lanes
- SST or MST operation
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DisplayPort Transmitter & Receiver
- Compliant to Display Port 2.0/eDP1.5.
- Dynamic support for RGB / YCbCr444 / YCbCr422 / RAW and Y only formats.
