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DDR3 IP

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Compare 17 DDR3 IP from 10 vendors (1 - 10)
  • DDR2 & DDR3 Fault Tolerant Memory Controller
    • Configurable to have multiple AHB ports with concurrent accesses to different memory banks
    • 96-, 64- or 32-bits interface towards SDRAM
    Block Diagram -- DDR2 & DDR3 Fault Tolerant Memory Controller
  • DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
    • Interface: SSTL
    • Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1600Mbps
    • Data path width scales in 8-bit increment
    • Programmable output impedance
    Block Diagram -- DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
  • DDR-I/II/III CONTROLLER IP CORE
    • Compliant with JEDEC Standard.
    • Support up to 4 Gb and 8 banks of DDR2 devices.
    • Application bus – FIFO, AHB, Avalon. Support multiple agents on application bus interface with built-in credit/aging based weighted round robin arbitration scheme.
    • Programmable CAS latency and DRAM timing parameters.
    Block Diagram -- DDR-I/II/III CONTROLLER IP CORE
  • DDR3 Memory Controller
    • Maximizes bus efficiency via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
    • Minimal latency achieved via parameterized pipelining
    • Achieves high clock rates with minimal routing constraints
    • Supports full rate and half-rate clock operation
  • DDR3 Controller IP
    • o High memory throughput achieved via Parallel operation of all the banks and reordering of commands in the controller to ensure the maximum utilization of the DDR Memory
    • o Pipelined operation across the complete design to ensure the highest performance
    • o DDR Interface
    • o Supports all standard DDR3 (x4,x8,x16) SDRAMs
  • DDR3L Memory Controller IP optimized for low latency
    • DDR3L interface provides full support for the DDR3L
    • Supports DDR3L protocol standard of interface, compatible with DDR3L protocol standard
    • of 8GB_DDR3L and DFI-version 3.1 or higher
    • Compliant with DFI-version 3.1 or higher
  • DDR3 SDRAM Controller IP with advance feautures package
    • Supports DDR3 protocol standard JESD79-3F Specification.
    • Compliant with DFI-version 2.0 or higher Specification.
    • Supports all the DDR3 commands as per the specs. Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
  • DDR Memory Controller IP for low power and high reliability
    • Supports DDR protocol standard JESD79F Specification.
    • Compliant with DFI-version 2.0 or higher Specification.
    • Supports all the DDR commands as per the specs. Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
  • High Performance DDR 3/2 Memory Controller IP
    • Supports DDR3/DDR2 SDRAM
    • 16 bits width DDR2/DDR3 SDRAM Interface
    • Memory Clock up to 462MHz, DFI Clock up to 462MHz
    • Support DDR2 667/800/1066 and DDR3 667/800/1066/1333/1600/1866
  • DDR3L Controller IP
    • Supports DDR3L protocol standard of 8GB_DDR3L.pdf.
    • Compliant with DFI-version 3.1 or higher Specification.
    • Supports up to 8 GB device density.
    • Supports Programmable Write latency and Read latency.
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