DDR2 IP
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31
DDR2 IP
from 12 vendors
(1
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10)
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ONFI 3.2 NV-DDR2 PHY in GDSII
- Compliant to ONFI revision 3.2 standard
- Supports NV-DDR2 mode of operation supporting up to 266MHz or 566MT/s
- Supports NV-DDR mode of operation supporting up to 100MHz
- Supports legacy Asynchronous devices operating from 10MHz to 50MHz
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DDR2 Monitor Verification IP
- Supports DDR2 memory devices from all leading vendors
- Quickly validates the implementation of the DDR2 standard
- Constantly monitors DDR2 behavior during simulation
- Checks for following
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QDR2 Synthesizable Transactor
- Supports 100% of QDR2 protocol standard CY7C1314CV18
- Supports separate independent read and write data ports with concurrent read and write operation
- Supports full data coherency, providing most current data
- Supports synchronous pipeline read with self-timed late write
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GDDR2 Synthesizable Transactor
- Supports 100% of GDDR2 protocol standard
- Supports all the GDDR2 commands as per the specs
- Supports all types of timing and protocol violation detection
- Supports all mode registers programming
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DDR2 Synthesizable Transactor
- Supports 100% of DDR2 protocol standard JESD79-2F
- Supports all the DDR2 commands as per the specs
- Supports double data rate interface
- Supports up to 4 GB device density
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DDR2 DFI Verification IP
- Compliant with DFI version 2.0 or higher Specification.
- DFI-DDR2 Applies to :
- DDR2 protocol standard JESD79-2F Specification
- Supports all Interface Groups.
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DDR2 Memory Model
- Supports DDR2 memory devices from all leading vendors.
- Supports 100% of DDR2 protocol standard JESD79-2F.
- Supports all the DDR2 commands as per the specs.
- Supports double data rate interface.
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DDR2 DFI Assertion IP
- Specification Compliance
- Compliant with DFI version 2.0 or higher Specification.
- DFI-DDR2 Applies to :
- DDR2 protocol standard JESD79-2F Specification
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DDR2 Assertion IP
- Specification Compliance
- Compliant with DDR2 specifications.
- Supports all DDR2 data widths and address widths.
- Supports all DDR2 bank address widths.
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DDR Assertion IP
- Specification Compliance
- Quickly validates the implementation of the DDR standard
- Checks for following
- Check-points include power on, Initialization and power off rules,