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USB 3.1 PHY IP

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Compare 28 USB 3.1 PHY IP from 7 vendors (1 - 10)
  • Complete USB Type-C Power Delivery PHY, RTL, and Software
    • USB PD 3.1 compliant.
    • 8 bit register interface for a low speed processor, or optional I2C interface.
    • Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
    Block Diagram -- Complete USB Type-C Power Delivery PHY, RTL, and Software
  • USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 55LL
    • Support half rate mode (5Gbps) and full rate mode (10Gbps)
    • Tolerate max +/-7000ppm input frequency offset
    • 32bit/40bit selectable parallel data bus
    • Programmable transmit amplitude
    Block Diagram -- USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 55LL
  • USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in SMIC 14SF+
    • Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
    • Supports 5.0Gbps and 10Gbps serial data transmission rate
    • Supports 16-bit or 32-bit parallel interface
    • Data and clock recovery from serial stream
    Block Diagram -- USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in SMIC 14SF+
  • USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
    • Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
    • Supports 5.0Gbps and 10Gbps serial data transmission rate
    • Supports 16-bit or 32-bit parallel interface
    • Data and clock recovery from serial stream
    Block Diagram -- USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
  • USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
    • Support half rate mode (5Gbps) and full rate mode (10Gbps)
    • Tolerate max +/-7000ppm input frequency offset
    • 32bit/40bit selectable parallel data bus
    • Programmable transmit amplitude
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
  • USB 3.0 PHY IP, Silicon Proven in TSMC 28HPC+
    • Compliant with Universal Serial Bus 3.0 Specification
    • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
    • Compliant with PIPE 3.0
    • Compliant with Universal Serial Bus 2.0 Specification
    Block Diagram -- USB 3.0 PHY IP, Silicon Proven in TSMC 28HPC+
  • USB-C 3.1 DP/TX PHY ebdaux in TSMC (N5, N3E)
    • Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
    • Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
    • Configurable data buffering options to optimize performance vs area
    • Supports all USB speed modes
  • USB 3.1 PHY (10G/5G) inTSMC (16nm, 12nm, N7, N6, N5,N3E)
    • Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
    • Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
    • Configurable data buffering options to optimize performance vs area
    • Supports all USB speed modes
  • USB-C 3.1/DP TX PHY in GF (22nm)
    • Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
    • Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
    • Configurable data buffering options to optimize performance vs area
    • Supports all USB speed modes
  • USB 3.1 PHY (10G/5G) in GF (22nm)
    • Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
    • Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
    • Configurable data buffering options to optimize performance vs area
    • Supports all USB speed modes
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