Serial RapidIO - Physical Layer Interface
Overview
The Serial RapidIO core supports the physical layer specification as defined in the RapidIO Specification Rev 1.2. The Serial RapidIO Physical Layer defines a protocol for packet delivery between Serial RapidIO devices and other devices, including packet transmission, flow control, error management and link maintenance protocols. The core supports one-lane high speed (1x mode) running at 1.0, 2.0 Gbps or a maximum of 2.5 Gbps. This Serial RapidIO core is optimized to support ORT82G5/ORT42G5 FPSCs.
Key Features
- Supports High Speed 1x Mode (up to 2.5 Gbps)
- 8B/10B Encoding and Decoding
- Clock and Data Recovery (CDR)
- Lane Synchronization
- CRC Generation and Checking
- Error Detection
- Packet/Control Symbol Assembly and De-assembly
- Simple User Interface for Easy Integration into User Logic
- Targets ORT82G5/ORT42G5 FPSC
Block Diagram
Technical Specifications
Related IPs
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- Multi-Rate Serial Digital Interface (SDI) PHY Layer
- PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
- Physical Layer Interface Core
- v5.2 Link Layer, Physical Layer, Software Stack and Profiles for Bluetooth low energy
- Serial RapidIO Controller