MIPI A-PHY IP
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MIPI A-PHY IP
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MIPI A-PHY IP
from 4 vendors
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5)
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MIPI A-PHY Verification IP
- Implemented in native OpenVera, SystemVerilog, Verilog and SystemC.
- Supported RVM, AVM, VMM, OVM, UVM and non-standard verify env.
- Supports MIPI A-PHY specification version upto 2.0.
- Supports single lane and dual lane, point-to-point and serial communication technology.
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A-PHY v1.1 Verification IP
- Compliant to MIPI A-PHY Specification Version 1.1.1 with APPI interface.
- Support all C-Port, D-Port and Q-Port.
- Support for both Profile 1 and Profile 2.
- Supports all possible configuration for Data Lane Module at PHY layer.
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Automotive MIPI A-PHY Source IP - 1-Lane
- Compliant with MIPI A-PHY specification version 1.0
- Support Gear-2 up to 4Gbps
- Support data bus width: 20-bit parallel interface
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Automotive MIPI A-PHY Sink IP (2-Lane)
- Compliant with MIPI A-PHY specification version 1.0
- Support Gear-2 up to 4Gbps