LPDDR IP for UMC
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LPDDR IP
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4
LPDDR IP
for UMC
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LPDDR4 multiPHY V2 - UMC 28HPC+18
- Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
- Support for data rates up to 4,267 Mbps (process dependent)
- Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
- PHY independent, firmware-based training using an embedded calibration processor
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LPDDR5X/5/4X/4 Combo PHY & Controller
- LPDDR5 and LPDDR4/4X modes & signaling, rates from 20Mbps up to 8533Mbps (LPDDR5/5X) and 4266Mbps (LPDDR4/4X), respectively
- x16/x32/x64 data path interface extendable
- 1.05V/1.1V JEDEC IO standard, support 1.05V and 1.1V LVSTL I/Os
- support LPDDR4X 0.6V IO voltage and LPDDR5 0.5V/0.3V IO voltage