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Memory Interface IP for UMC

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Compare 122 Memory Interface IP for UMC from 8 vendors (1 - 10)
  • DDR4 multiPHY - UMC 28HPC18
    • Support for JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAMs
    • Scalable architecture that supports data rates up to DDR4-2667
    • Support for DIMMs
    • Delivery of product as a hardened mixed-signal macrocell component allows precise control of timing critical delay and skew paths
    Block Diagram -- DDR4 multiPHY - UMC 28HPC18
  • LPDDR4 multiPHY V2 - UMC 28HPC+18
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4 multiPHY V2 - UMC 28HPC+18
  • ONFI IO v3.2, 533MT/s, UMC40LP
    • Supports ONFI 6.0(4.8Gbps), ONFI 5.1(3.6Gbps), ONFI 5.0(2.4Gbps), ONFI 4.1(1.2Gbps), ONFI 4.0(800Mbps) & ONFI 3.2(533Mbps)
    • Power-sequence free
    • Provides multi-driving-strength selection
    • Provides CTT mode and LTT mode
    Block Diagram -- ONFI IO v3.2, 533MT/s, UMC40LP
  • ONFI IO v3.2, 533MT/s, UMC 28HPC+, 1.8V, N/S orientation, H&V cell
    • Supports ONFI 6.0(4.8Gbps), ONFI 5.1(3.6Gbps), ONFI 5.0(2.4Gbps), ONFI 4.1(1.2Gbps), ONFI 4.0(800Mbps) & ONFI 3.2(533Mbps)
    • Power-sequence free
    • Provides multi-driving-strength selection
    • Provides CTT mode and LTT mode
    Block Diagram -- ONFI IO v3.2, 533MT/s, UMC 28HPC+, 1.8V, N/S orientation, H&V cell
  • ONFI IO v4.0, 800MT/s, UMC 28HPC+, 1.8V, N/S orientation, H&V cell
    • Supports ONFI 6.0(4.8Gbps), ONFI 5.1(3.6Gbps), ONFI 5.0(2.4Gbps), ONFI 4.1(1.2Gbps), ONFI 4.0(800Mbps) & ONFI 3.2(533Mbps)
    • Power-sequence free
    • Provides multi-driving-strength selection
    • Provides CTT mode and LTT mode
    Block Diagram -- ONFI IO v4.0, 800MT/s, UMC 28HPC+, 1.8V, N/S orientation, H&V cell
  • ONFI IO v4.1, 1.2T/s, UMC 22ULL, 1.8V, N/S orientation, H&V cell
    • Supports ONFI 6.0(4.8Gbps), ONFI 5.1(3.6Gbps), ONFI 5.0(2.4Gbps), ONFI 4.1(1.2Gbps), ONFI 4.0(800Mbps) & ONFI 3.2(533Mbps)
    • Power-sequence free
    • Provides multi-driving-strength selection
    • Provides CTT mode and LTT mode
    Block Diagram -- ONFI IO v4.1, 1.2T/s, UMC 22ULL, 1.8V, N/S orientation, H&V cell
  • DDR4 multiPHY in UMC (28nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard DDR4 up to 2667 Mbps
    • Compatible with JEDEC standard DDR3 SDRAMs up to 2133 Mbps
    • Compatible with JEDEC standard LPDDR2 SDRAMs up to 1066 Mbps
  • SATA 6G PHY in UMC (40nm, 28nm, 22nm)
    • Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
    • AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
    • AMBA 4 AXI and ACE-Lite bus interfaces
    • Memory data protection and memory address parity protection
  • Denali High-Speed DDR PHY for UMC
    • LPDDR4/LPDDR3/DDR4/DDR3/DDR3L training with write-leveling and data-eye training
    • I/O pads with impedance calibration logic and data retention capability
    • Optional clock gating available for low-power control
    • Multiple PLLs for maximum system margin
  • Serial ATA (SATA) I/II PHY IP CORE
    • Supports 1.5 Gb/s (Gen 1) and 3.0 Gb/s (Gen 2) serial data rate
    • Compatible with Serial ATA II
    • Utilizes 10-bit or 20-bit parallel interface to transmit and receive Serial ATA data
    • Data and clock recovery from serial stream on the SATA bus
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