USB IP for TSMC

Compare 144 USB IP for TSMC from 13 vendors (1 - 10)

USB 3.1 Cable Marker IP
- USB PD 3.1 compliant.
- Single chip solution – just two external capacitors.
- 4 pin package.
- Less than 1mm2 area in 180nm.
- PROM programmed through vendor message protocol.
- Based on Obsidian’s mature PD technology.
- Integrated PROM enables customized response to a wide range of vendor requirements.
- Active Ra pulls down only requires 10uA at 5V., but is <1K below 2V.
- Power <5mW. Enabled by CC data activity. I.e. very low duty cycle.
- Programming can be done after assembly into the cable. Fuse lock function.
- Supports low cost, 4 layer PCB assembly.
Complete USB Type-C Power Delivery IP
- Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
- RTL code from AFE to I2C compatible register set.
- Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
- IP demonstration & development board, with compliance reports.
- Full chip integration of USB Type-C, and associated software.
USB 2.0 PHY
- Designed to the USB 2.0 specification, and operates at High Speed (480Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps)
- Complies with the UTMI v1.05 specification
- Multiple reference clock supported from 9.6MHz up to 52MHz
- 8-bit 60MHz and 16-bit 30MHz parallel interfaces
- Battery Charging Specification v1.2
USB 2.0 Host Controller
- Fully compliant with USB Specification rev 2.0.
- Host Controller supports high (480 Mbps), full (12 Mbps) and low (1.5 Mbps) speed operation
- USB host controller supports Control, Bulk, Isochronous and Interrupt transactions
- VCI interface to external host processor
USB 2.0 Device Controller
- Full Compliance with the USB 2.0 specification.
- Control Endpoint 0 - Fixed size of 64-bytes.
A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell
- GPIO:
- I2C / SMBUS Open-Drain I/O:
- LVDS
- ANALOG
A 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
- GPIO:
- I2C / SVID Open-Drain I/O:
- ANALOG
- OTP Programming Cell
USB 2.0 femtoPHY -TSMC N6 18 x1, OTG, North/South (vertical) poly orientation
- Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
- Supports the USB 2.0 protocol and data rate (480 Mbps)
- Supports the USB Type-C specification
- USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
USB 2.0 femtoPHY - TSMC N5 12 x1, North/South (vertical) poly orientation
- Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
- Supports the USB 2.0 protocol and data rate (480 Mbps)
- Supports the USB Type-C specification
- USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
USB 2.0 femtoPHY - TSMC N3P 1.2V x1, North/South (vertical) poly orientation
- Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
- Supports the USB 2.0 protocol and data rate (480 Mbps)
- Supports the USB Type-C specification
- USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design