Building Blocks IP for TSMC

Compare 7 Building Blocks IP for TSMC from 5 vendors (1 - 7)

Fully Configurable Radix 2 FFT/IFFT Processor
- Radix-2 Fast Fourier Transform processor IP Core.
- Same IP core may be used to compute both FFT and IFFT transforms without any complexity overhead.
- Highly parameterizable/scalable design using generic I/O fixed point precision and generic internal calculations precision.
- Bit true Matlab script model is provided to aid core fixed point precision configuration for any target application.
12-bit 250MHz interpolation filter with 43 taps
- Programmable Coefficients
- Programmable gain/attenuation at the output
- 4X Decimation Factor
12-bit 250MHz Decimation filter with 43 taps
- Programmable Coefficients
- Programmable gain/attenuation at the output
- 4X Decimation Factor
Fast Fourier Transformation
- The FFT is a fully customizable FFT. The key features are free choose of the FFT dimension, data width and an additional output with the absolute value of the spectrum.
SPDIF-Tx-Pro : Configurable SPDIF/AES3 Transmitter
- Supports the IEC60958 (SPDIF) and AES3 standards for PCM audio transmission
- Supports the IEC61937, SMPTE 337M standards for non-PCM audio transmission
- Automatic insertion of Validity bits in non-PCM mode
- Supports any sample rate Fs by setting the audio clock frequency to 256*Fs including 32, 44.1, 48, 96 and 192 kHz
SPDIF-Rx-Pro : Configurable SPDIF-AES/EBU Receiver
- Supports the IEC60958 (SPDIF), AES3 standards for PCM audio transmission
- Supports the IEC61937, SMPTE 337M standards for non-PCM (ie, compressed) audio transmission
- Uses a single domain clock frequency, unrelated to the sample frequency
- Supports up to 24 bits per sample
Multi-Channel Signature Calculator
- Works on several data blocks in parallel
- Configurability: packet size, number of windows, internal memory parameters
- AXI interfaces for data and control
- DMA results write-out