MIPI DSI IP for SMIC
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MIPI DSI IP
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MIPI DSI IP
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MIPI D-PHY DSI RX (Receiver) in SMIC 130nm
- SMIC 130nm
- Consists of 1 Clock lane and 4 Data lanes
- Supporting the MIPI Standard 1.1 for D-PHY
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MIPI D-PHY Universal IP
- Complies with MIPI Standard for D-PHY V1.0
- Point-to-point differential interface supporting multiple data lanes and a clock lane
- Supports both high speed and low-power modes
- Data lanes support both bidirectional and unidirectional modes
