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Interconnect IP for Samsung

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Search (174)
Compare 174 Interconnect IP for Samsung from 12 vendors (1 - 10)
  • 1-112Gbps Integrated Laser Driver and Optical SerDes
    • Optical Optimization:
    • Integrated laser driver
    • RX front-end architected for optical signaling
    • Non-linear DSP equalization that corrects for both static and dynamic nonlinearity components.
    Block Diagram -- 1-112Gbps Integrated Laser Driver and Optical SerDes
  • 1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
    • High speed performance
    • Low power architecture
    • Sub-sampling clock multiplier
    Block Diagram -- 1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
  • MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 5nm
    • Low power consumption, small area
    • Supports both overdrive (0.85V) and normal (0.75V) power
    • Support for various lane configurations
    Block Diagram -- MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 5nm
  • MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 4nm
    • Samsung Foundry 4nm low power enhanced (LN04LPE) CMOS device technology
    • 1.2V±5%, 0.75/0.85V±5% power supply
    Block Diagram -- MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 4nm
  • MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 5nm
    • Samsung Foundry 5nm low power enhanced (LN05LPE) CMOS device technology
    • 1.8V±5%, 1.2V±5%, 0.75/0.85V±5% power supply
    Block Diagram -- MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 5nm
  • USB 3.1 PHY
    • Supports USB 3.1, PCIe 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSGMII/SGMII
    • Multi-protocol support for simultaneous independent links
    • Supports SRIS and internal SSC generation
    • Supports PCIe L1 sub-states
    • Automatic calibration of on-chip termination resistors
    Block Diagram -- USB 3.1 PHY
  • eUSB2V2 PHY
    • Up to 4.8Gbps scalable data rate
    • Compliant to eUSB2V2 r1.0 / UTMI2.0 r0.9
    • Configurable to Host or Peripheral
    • Supports L1/L2 low power state
    • Supports eUSB2V2 Compliance Modes and RxMargining Mode
    • Support 19.2/24/48/100 MHz Ref Clocks
    Block Diagram -- eUSB2V2 PHY
  • PHY for PCIe 6.0 and CXL
    • Architecture optimized for HPC, AI/ML, storage, and networking
    • Ultra-long reach, low latency, and low power
    • Advanced DSP delivers unmatched performance and reliability
    • Comprehensive real-time diagnostic, monitor, and test features
    • Bifurcation support for x1, x2, x4, x8, and x16 lanes
    Block Diagram -- PHY for PCIe 6.0 and CXL
  • PHY for PCIe 4.0 - Low-power, long-reach, multi-protocol PHY for PCIe 4.0
    • Wide range of protocols that support networking, high-performance computing (HPC), and applications
    • Low-latency, long-reach, and low-power modes
    • Multi-Link PHY—mix protocols within the same macro
    • EyeSurf —non-destructive on-chip oscilloscope
    • User-friendly graphical interface provides easy access to embedded bit-error-rate (BER) and pattern testers and monitors to measure the link performance in real time
    Block Diagram -- PHY for PCIe 4.0 - Low-power, long-reach, multi-protocol PHY for PCIe 4.0
  • MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 Samsung 28nm FD-SOI
    • 4 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of Samsung 28nm FD-SOI process
    Block Diagram -- MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 Samsung 28nm FD-SOI
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