NPU IP for Embedded AI

Overview

Key Features

• Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
• Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
• Future proof architecture that supports the most advanced ML data types and operators
  • 4-bit to 32-bit integer support
  • Native transformer computation
• Ultimate ML performance for all use cases
  • Acceleration of sparse model inference (sparsity acceleration)
  • Acceleration of non-linear activation types
  • Fast quantization – up to 5 times acceleration of internal re-quantizing tasks
• Ultra-low memory requirements achieved with Ceva-NetSqueeze™
  • Up to 80% memory footprint reduction through direct processing of compressed model weights without need for intermediate decompression stage
  • Solves a key bottleneck inhibiting the broad adoption of AIoT processors today
• Ultra-low energy achieved through innovative energy optimization
  • Dynamic Voltage and Frequency Scaling support - tunable for the use-case
  • Dramatic energy and bandwidth reduction by distilling computations using weight-sparsity acceleration
• Complete, simple to use Ceva NeuPro-Studio AI SDK
  • Optimized to work seamlessly with leading, open-source AI inference frameworks, such as TFLM and µTVM
  • Model Zoo of pre-trained and optimized machine learning models covering TinyML voice, vision and sensing use cases.
  • Comprehensive portfolio of optimized runtime libraries and off-the-shelf application-specific software
• Two NPU configurations to address a wide variety of use cases
  • Ceva-NPN32 with 32 4x8, 32 8x8, 16 16x8, 8 16x16, 4 32x32 MPY/MAC operations per cycle
  • Ceva-NPN64 with 128 4x8, 64 8x8, 32 16x8, 16 16x16, 4 32x32 MPY/MAC operations per cycle and 2x performance acceleration using 50% weight sparsity (Sparsity Acceleration)

Benefits

• The NPU family is specially designed to bring the power of AI to the Internet of Things (IoT), through efficient deployment of Tiny Machine Learning (TinyML) models on low-power, resource-constrained devices.
• Fully programmable and efficiently executes Neural Networks, feature extraction, control code and DSP code
• Supports most advanced machine learning data types of 4,8,16, and 32-bit, and many operators including native transformer computation, fast quantization and sparsity support with weight decompression and acceleration
• Self-sufficient architecture enables  NPUs to deliver superior power efficiency, with a smaller silicon footprint, and optimal performance

Block Diagram

Technical Specifications