The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional mode.
? The D-PHY is built in with a standard digital interface to talk to any third-party host controllers.
? The C-PHY is designed to coexist on the same IC pins as D-PHY so that dual-mode devices could be developed with low power signaling similar to D-PHY.
The D-PHY and C-PHY support the electrical portion of MIPI D-PHY V1.2 standard and MIPI C-PHY V1.1 standard, covering all transmission modes (ULP/LP/HS). Innosilicon MIPI C/D PHY TX enables a seamless implementation allowing interfaces to D-PHY based sensors or C-PHY based sensors. This IP cost-effectively adds MIPI D-PHY and MIPI C-PHY capability to any SoC used in communication and consumer electronics field.
The Innosilicon I/O and ESD are also built-in as one in a rectangular footprint for any configuration. It is optimized for high-speed applications with robust timing and small silicon area.
MIPI DPHY2.0/CPHY1.1 TX (support combo TTL, LVDS, HiSPI)
Overview
Key Features
- Analog mixed-signal hard-macro HS/LP transmitter solution
- Compliant with MIPI® Alliance Specification for D-PHY V1.2
- Compliant with MIPI® Alliance Specification for C-PHY V1.1
- Integrated PHY Protocol Interface (PPI) supports interfaces to CSI, DSI and UniPro™ MIPI® protocols
- HS, LP, ULPS modes supported
- 2.5Gbps maximum data transfer rate per lane on D-PHY mode
- 2.5Gsps maximum data transfer rate per trio on C-PHY mode
- Asynchronous transfer at low power mode with a bit rate of 10Mbps on both C-PHY and D-PHY
- Unidirectional and bi-directional modes supported
- Skew-calibration for D-PHY supported
- ECC and CRC insertion supported
- Automatic termination control for HS and LP modes
- Buffers with tunable on-die-termination and advanced equalization
- Embedded bump pads
- Supports PHY BIST logic
Deliverables
- Databook and detailed physical implementation guides for the complete PHY
- Library Exchange Format (LEF) file with pin size and locations
- Gate-level netlist and Standard Delay Format (SDF) Timing file
- Layout Versus Schematic (LVS) flattened netlist in spice format and report
- Encrypted Verilog Models
- GDSII database for foundry merge
- Module integration guidelines
- Silicon validation report (when available)
- Evaluation board (when available)
Technical Specifications
Foundry, Node
TSMC 6/3nm, GF 14/12nm, SMIC 14nm
GLOBALFOUNDRIES
Silicon Proven:
12nm
,
14nm
LPP
SMIC
Pre-Silicon:
14nm
TSMC
Silicon Proven:
3nm
,
6nm
Related IPs
- MIPI DPHY1.2 RX (support combo TTL, LVDS, HiSPI)
- LVDS TX Combo TTL PHY
- LVDS Transmitter 1250Mb/s, 800Mhz clock with RSDS support
- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY/sub-LVDS combo Transmitter 1.5G/1.0Gbps 4-Lane