IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI PHY IP > MIPI D-PHY IP > MIPI D-PHY TX Combo TTL PHY

MIPI D-PHY TX Combo TTL PHY

Overview

The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional mode.
The D-PHY is built in with a standard digital interface to talk to any third-party Host controller.
This enables a seamless implementation allowing interfaces to D-PHY based sensors. The Innosilicon I/O and ESD are also built-in as one in a rectangular footprint for any configuration. It is optimized for High-speed applications with robust timing and small silicon area.
The D-PHY supports the electrical portion of MIPI D-PHY V1.2 standard, covering all transmission modes (ULP/LP/HS). This IP cost-effectively adds MIPI D-PHY capability to any SoC used in communication and consumer electronics field.

Key Features

  • Analog mixed-signal hard-macro HS/LP transmitter solution
  • Compliant with MIPI® Alliance Specification for D-PHY V1.2
  • Integrated PHY Protocol Interface (PPI) supports interfaces to CSI, DSI and UniPro™ MIPI® protocols
  • HS, LP, ULPS, and TTL modes supported
  • 2.5Gbps maximum data transfer rate per lane on D-PHY mode
  • 200Mbps maximum data transfer rate per pad on TTL mode
  • Asynchronous transfer at low power mode with a bit rate of 10Mbps in D-PHY mode
  • Unidirectional and bi-directional modes supported
  • Skew-Calibration for D-PHY supported
  • Automatic termination control for HS and LP modes
  • Buffers with tunable On-Die-Termination and advanced equalization
  • Embedded bump pads
  • Supports PHY BIST logic

Deliverables

  • Databook and detailed physical implementation guides for the complete PHY
  • Library Exchange Format (LEF) file with pin size and locations
  • Gate-level netlist and Standard Delay Format (SDF) Timing file
  • Layout Versus Schematic (LVS) flattened netlist in spice format and report
  • Encrypted Verilog Models
  • GDSII database for foundry merge
  • Module integration guidelines
  • Silicon validation report (when available)
  • Evaluation board (when available)

Technical Specifications

Foundry, Node
UMC 40LP
UMC
In Production: 40nm LP
Silicon Proven: 40nm LP
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