MIPI C-PHY/D-PHY Combo CSI-2 TX 3.5Gsps/trio in TSMC 28nm

Overview

The MXL-CDPHY-3p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5 and C-PHY v2.0. The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications.

Key Features

Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
Consists of 3 Data lanes in C-PHY mode
Embedded, high performance, and highly programmable PLL
PLL supports SSC mode, Fractional mode, and Integer mode
Supports both low-power mode and highspeed mode with integrated SERDES
80 Mbps to 1.5 Gbps data rate per lane without skew calibration in D-PHY mode
3.5 Gbps data rate per lane with skew calibration in high speed D-PHY mode
80 Msps to 3.5 Gsps symbol rate per lane in high speed C-PHY mode
Supports High Speed TX De-emphasis Equalization
10 Mbps data rate in low-power mode
Low power dissipation
Testability support
Calibrator for resistance termination

Benefits

Compatible with both C-PHY v2.0 and D-PHY v2.5 specifications for added flexibility.

Block Diagram

Applications

Mobile
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC, CRN28HT

Maturity

Available Upon Request

Availability

Now

TSMC

Pre-Silicon: 28nm

Request Info