IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI PHY IP > MIPI C-PHY/D-PHY Combo IP > MIPI C/D-PHY RX

MIPI C/D-PHY RX

Overview

The Innosilicon MIPI C/D-PHY RX provides D-PHY and C-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, plus a MIPI® low-power low speed receiver that supports data transfer in the bi-directional mode.
? The D-PHY is built in with a standard PPI digital interface to talk to any third-party Host controller.
? The C-PHY was designed to coexist on the same IC pins as D-PHY so that dual-mode devices could be developed with low power signaling similar to D-PHY.
This enables a seamless implementation allowing interface to D-PHY based sensors or C-PHY based sensors. The Innosilicon I/O and ESD are also built-in as one in a rectangular footprint. It is optimized for high speed applications with robust timing and small silicon area.
The D-PHY and C-PHY support the electrical portion of MIPI D-PHY V1.2 standard and C-PHY V1.1 standard, covering all transmission modes (ULP/LP/HS). This IP cost-effectively adds MIPI D-PHY V1.2 and MIPI C-PHY V1.1 capability to any SoC used in communication and consumer electronics field.

Key Features

  • Analog mixed-signal hard-macro LP/HS receiver solution
  • Compliant with MIPI Alliance Standard for C-PHY Specifications V1.1
  • Compliant with MIPI Alliance Standard for D-PHY Specifications V1.2
  • Integrated PHY Protocol Interface (PPI) supports interfaces to make connection to CSI-2, DSI-2 and UniPro™ MIPI® protocols
  • HS, LP, ULPS modes supported
  • 2.5Gsps maximum data transfer rate per trio on C-PHY mode
  • 2.5Gbps maximum data transfer rate per lane on D-PHY mode
  • Asynchronous transfer at low power mode with a bit rate of 10Mbps on both C-PHY and D-PHY supported
  • Unidirectional and bi-directional modes supported
  • Auto/Manual-deskew supported
  • ECC and CRC insertion supported
  • Automatic termination control for HS and LP modes
  • Low-Power dissipation: less than 2mA per trio/lane in C/D-PHY HS RX mode
  • Buffers with tunable On-Die-Termination
  • Embedded bump pad
  • PHY BIST logic supported

Deliverables

  • Databook and physical implementation guides Netlist (Spice format for LVS)
  • Library Exchange Format (LEF)
  • Encrypted Verilog Models
  • GDSII to Foundry IP Merge
  • Module integration guidelines
  • Silicon validation report (when available)
  • Evaluation board (when available)

Technical Specifications

Foundry, Node
Samsung 5nm, TSMC 6nm, GF 14/12nm, SMIC 14nm
GLOBALFOUNDRIES
In Production: 12nm , 14nm LPP
Silicon Proven: 12nm , 14nm LPP
SMIC
In Production: 14nm
Silicon Proven: 14nm
Samsung
In Production: 5nm
Silicon Proven: 5nm
TSMC
In Production: 6nm
Silicon Proven: 6nm
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