INNOLINK-C Controller

Overview

The INNOLINK-C Controller (hereinafter referred to as “ILC”) combined with INNOLINK-C PHY is a complete solution for high-speed data communication between dies or chips. INNOLINK-C IP is a GDDR-like, single ended IP, providing data rate of up to 24Gbps/pin, for typical MCM or short PCB applications.
The ILC can support interface access through the APL bus interfaces, while the register interface is connected to the ILC through the standard APB bus interfaces.
The ILC issues commands compliant with the DFI protocol through the DFI interface to the PHY module, transmitting/receiving command/data to/from the other die.

Key Features

General Features
- Operating frequency no less than 1.5GHz
- Provides user-defined FLIT APL interface
- Message CRC32 generation and verification
- Message FEC RS (255,249) generation and correction
- Error message resend (based on FEC-CRC-SEQ sequence number)
- TX payload content PRSB31 with self-framing
- RX payload content PRSB31 with self-detection
- DFI interface message loopback
- User-defined test message generation
- PVT retraining trigger
- Low Power
DFI Features
- Supported
  - All typical control, write data and read data interface signals
- Unsupported
  - CtrlUpd interface
  - PhyMstr interface
  - Controller training mode
  - DFI disconnect protocol
- APL Interface Features
  - Unsupported
    - Exclusive access support
  - AXI Interface Features
    - Supported
      - Compatibility with the AMBA 4 AXI4 and AMBA 3 AXI protocols
      - Support for AXI burst types: fix, incremental and wrap
      - AXI clock asynchronous/synchronous to the controller clock
    - Unsupported
      - AXI QOS
      - Exclusive access support
    - APB Interface Features
      - Supported
        
        APB 3.0
      - Unsupported
        
        APB 2.0

Benefits

Available in any 40nm or below technology nodes
Significantly lower cost, shorter time to market, lower supply risks for OEMs and simpler architectural partitioning than the monolithic silicon integration
Offers leading performance, power, and area per terabit
Flexible configuration with support for silicon interposer, package substrate and PCB options
Customizable synthesis for any FPGAs and ASICs
Full support from IP delivery to production

Applications

High performance computing (HPC) applications
Next-generation data center
Networking
5G communication
Artificial intelligence / machine learning (AI/ML) applications

Deliverables

Data book, Application notes
Verilog Getech File
SDC File
Simulation environment and user guide

Technical Specifications

Foundry, Node

TSMC, Samsung, SMIC, Global Foundies

Availability

now

SMIC

Pre-Silicon: 14nm

Samsung

Pre-Silicon: 14nm

TSMC

In Production: 12nm
Silicon Proven: 12nm

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