HBM3/2E Combo PHY&Controller

Overview

The third-generation HBM (HBM3/2E) technology, outlined by the JESD235C standard, inherits physical 128-bit DDR interface with 2n/4n prefetch architecture, internal organization, 1024-bit input/output, 1.2 V I/O and core voltages as well as all the crucial parts in the original technology. Just like the predecessor, HBM3/2E supports two, four, eight or twelve DRAM devices on a base logic die (2Hi, 4Hi, 8Hi, 12Hi stacks) per KGSD. HBM Gen 3 expands the capacity of DRAM devices within a stack to 24GB and increases the data rate by up to 7.2Gb/s per pin. In addition, the new technology brings an important improvement to bandwidth maximization.

The INNO HBM3/2E is part of Innosilicon’s broad leading-edge memory IP portfolio that includes GDDR6/6X and DDR5/LPDDR5. Developed by the experienced team with great expertise, the Innosilicon product family enables customers to achieve the best design results while accelerating time to market.

Key Features

Compliant with JEDEC Specification, up to 6400Mbps for HBM3 mode, 3600Mbps for HBM2E mode
Compliant with DFI 3.1 Specifications (dfi_clk_1x: WDQS = 1:4 for HBM3 Mode, dfi_clk_1x: WDQS = 1:2 for HBM2E Mode)
For HBM3 mode, support up to 16 channels with 64 DQ-width + Optional DBI/ECC/SEV pin support/channel
For HBM2E mode, support up to 8 channels with 128 DQ-width
Supports command and DQ parity
Supports per-AWORD de-skew tuning for command
Supports bit-group de-skew tuning for data
Supports CMD lane repair
Supports DQ lane repair
Supports automatic and soft command bus training
Supports command and data IO driver strength adjustment
Supports automatic and soft RX DQS training and bypass RX DQS control
Supports automatic and soft WDQS2CK training (only for HBM3 mode) and bypass WDQS2CK Control
Supports automatic and soft read training
Supports automatic and soft write training
Supports bypass write and read trainings
Supports ZQ calibration
Supports Built-In Self-Test
Supports boundary scan of pad
Supports scan chain
APB 3.0 interfaces to configure registers
Supports IEEE1500 port for direct access to the memory stack and PHY using APB
Supports HBM DRAM initialized by PHY

Benefits

Substantially increases bandwidth available to computing devices
Fully pre-assemble design, drop-in hard macro to ease integration and speed time to market
Offers leading performance, power, and area per terabit
Extensive EDA tool support for various design automation flows
DFT functions to reduce test time and ensure high test coverage
Proven capabilities in PHY and silicon interposer design and integration
Optional PI/SI and thermal co-design service
Full support from IP delivery to production

Applications

High performance computing
Artificial intelligence
GPU

Deliverables

Verilog models
LEF
Place-and-route abstracts
GDSII files
LVS netlists
Optional extracted HSPICE netlist for I/Os
Databook, Application notes
Silicon validation and ESD testing results
Optional PCB reference design and Package Electrical Model
Documentation

Technical Specifications

Foundry, Node

Samsung 5nm

Maturity

Silicon Proven

TSMC

In Production: 5nm
Pre-Silicon: 5nm
Silicon Proven: 5nm

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